`timescale 1ns / 1ps

module sim_sel;

	// Inputs
	reg EN_L;
	reg Sel;
	reg D00;
	reg D01;
	reg D02;
	reg D03;
	reg D10;
	reg D11;
	reg D12;
	reg D13;

	// Outputs
	wire Y0;
	wire Y1;
	wire Y2;
	wire Y3;

	// Instantiate the Unit Under Test (UUT)
	xmjselector uut (
		.EN_L(EN_L), 
		.Sel(Sel), 
		.D00(D00), 
		.D01(D01), 
		.D02(D02), 
		.D03(D03), 
		.D10(D10), 
		.D11(D11), 
		.D12(D12), 
		.D13(D13), 
		.Y0(Y0), 
		.Y1(Y1), 
		.Y2(Y2), 
		.Y3(Y3)
	);

	initial begin
		EN_L=1;
		Sel=0;
		{D03,D02,D01,D00}=0;
		{D13,D12,D11,D10}=0;
		
		#100;
		{D03,D02,D01,D00}=15;
		{D13,D12,D11,D10}=15;
		
		#100;
		EN_L=0;
		{D03,D02,D01,D00}=4;
		{D13,D12,D11,D10}=0;
		
		#100;
		{D03,D02,D01,D00}=7;
		{D13,D12,D11,D10}=12;
		
		#100;
		Sel=1;
		{D03,D02,D01,D00}=8;
		{D13,D12,D11,D10}=5;
		
		#100;
		{D03,D02,D01,D00}=7;
		{D13,D12,D11,D10}=15;
	end
      
endmodule

